1. Field of the Invention
The present invention relates to digital device memory addressing techniques and systems and more particularly to an apparatus for translating virtual memory addresses into physical memory addresses.
2. Prior Art
Virtual memory schemes allow the expansion of a computer's memory capacity beyond the capacity of main memory. This scheme is typically accomplished by combining an expensive high-speed main memory with a low-cost lower speed secondary memory. Such a scheme has the advantage of allowing the use of a lengthy program without worrying about the hardware limitations of a given system. Hence, data storage hierarchies represent an effective compromise between a large, slow, inexpensive memory and a small, expensive one with high access speed. It is thus apparent that the cost benefits of such a scheme can be substantial whereby the efficient management of this structure presents a challenge.
Exemplary devices adapted to accomplish the above are called Memory Management Units, such as the NS16082 available from National Semiconductor of Santa Clara, Calif., the MC68451 available from Motorola Semiconductors of Austin, Tex., and the Z8010 available from Zilog Corporation of Cupertino, Calif.
A more detailed in-depth discussion of virtual memories, memory hierarchies and memory mapping is set forth in a book entitled Computer Structures: Principles and Examples by D. P. Siewiorek, et al, which was published in 1982 by the McGraw-Hill Book Company, at page 227, et seq. In addition, a more detailed description of the above-cited prior art devices is set forth in an article entitled "Virtual Memories for Microcomputers" by Stephen Schmitt, which was published in BYTE magazine of April, 1983, at page 210. Another article entitled "The National Semiconductor NS16000 Microprocessor Family" by Glenn Leedy, which was published in the same issue of BYTE at page 53, describes one of the prior art devices in detail. Finally, an article entitled "Design Trade-Offs in VAX-11 Translation Buffer Organization" by M. Satyanarayanan and D. Bhandarkar, which was published in an IEEE publication entitled Computer at page 103, describes a related virtual memory scheme.